Input/output peripheral equipment, including such computer items as printers, scanners, and display devices, require intermittent servicing by a host processor in order to ensure proper functioning. Services, for example, may include data delivery, data capture, and/or control signals. Each peripheral will typically have a different servicing schedule that is not only dependent on the type of device but also on its programmed usage. The host processor is required to multiplex its servicing activity amongst these devices in accordance with their individual needs while running one or more background programs. Two methods for advising the host of a service need have been used: polled device and device interrupt methods. In the former method, each peripheral device is periodically checked to see if a flag has been set indicating a service request, while, in the latter method, the device service request is routed to an interrupt controller that can interrupt the host, forcing a branch from its current program to a special interrupt service routine. The interrupt method is advantageous because the host does not have to devote unnecessary clock cycles for polling. It is this latter method that the present invention addresses. The specific problem addressed by the current invention is the management of interrupts in a multiprocessor system environment.
Multiprocessor systems, often a set of networked computers having common peripheral devices, create a challenge in the design of interrupt control methods. For instance, in the case of a computer network servicing a number of users, it would be highly desirable to distribute the interrupt handling load in some optimum fashion. Processors that are processing high priority jobs should be relieved of this obligation when processors with lower priority jobs are available. Processors operating at the lowest priority should be uniformly burdened by the interrupt servicing requests. Also, special circumstances may require that a particular I/O device be serviced exclusively by a pre selected (or focus) processor. Thus, the current invention addresses the problem of optimum dynamic and static interrupt servicing in multiprocessor systems.
Prior art, exemplified by Intel's 82C59A and 82380 programmable interrupt controllers (PICs), are designed to accept a number of external interrupt request inputs. The essential structure of such controllers, shown in FIG. 1, consists of six major blocks:
IRR: Interrupt Request Register 11 stores all interrupt levels (IRQx) on lines 16 requesting service; PA1 ISR: Interrupt Service Register 12 stores all interrupt levels which are being serviced, status being updated upon receipt of an end-of-interrupt (EOI); PA1 IMR: Interrupt Mask Register 13 stores the bits indicating which IRQ lines 16 are to be masked or disabled by operating on IRR11; PA1 VR: Vector Registers 19, a set of registers, one for each IRQ line 16, stores the preprogrammed interrupt vector number supplied to the host processor on data bus 17, containing all the necessary information for the host to service the request; PA1 PR: Priority Resolver 15, a logic block that determines the priority of the bits set in IRR11, the highest ;priority is selected and strobed into the corresponding bit of ISR12 during an interrupt acknowledge cycle (INTA) from the host processor; PA1 Control Logic: Control Logic 20 coordinates the overall operations of the other internal blocks within the same PIC, activates the host input interrupt (INT) line 21 when one or more bits of IRR11 are active, enables VR19 to drive the interrupt vector onto data bus 17 during an INTA cycle, and inhibits all interrupts with priority equal or lower than that being currently serviced. PA1 1) fully nested mode, PA1 2) automatic rotation--equal priority devices, made and PA1 3) specific rotation--specific priority mode. PA1 1) a separate Interrupt Bus, distinct from the memory (or system) bus, for communication of interrupt request (IRQ) and IRQ receipt acknowledgment signals, and for IRQ service arbitration between eligible servers; PA1 2) interrupt servicing of multiple I/O peripheral subsystems, each with its own set of interrupt lines; PA1 3) static as well as dynamic multiprocessor interrupt management; PA1 4) programmable interrupt vector and steering information for each IRQ pin; PA1 5) interprocessor interrupts allowing any processor to interrupt any other for dynamic reallocation of interrupt tasks; PA1 6) operating system defined programmable reallocation of interrupt tasks; and PA1 7) support of system-wide functions related to nonmaskable interrupt (NMIs), processor reset, and system debugging. PA1 1) an Interrupt Bus, separate and distinct from the memory (system) bus; PA1 2) an I/O interrupt delivery unit (IDU) connected to the Interrupt Bus and to a set of IRQ pins, having a redirection table for processor selection and interrupt priority and vector information; and PA1 3) a processor associated interrupt acceptance unit (IAU) connected to the Interrupt Bus for managing interrupt requests for a specific system processor including acceptance acknowledgment, IRQ pending, nesting and masking operations, and interprocessor interrupt management.
Several different methods have been used to assign priority to the various IRQ lines 16, including:
The fully nested mode, supports a multilevel interrupt structure in which all of the IRQ input lines 16 are arranged from highest to lowest priority: typically IRQ0 is assigned the highest priority, while IRQ7 is the lowest.
Automatic rotation of priorities when the interrupting devices are of equal priority is accomplished by rotating (circular shifting) the assigned priorities so that the most recently served IRQ line is assigned the lowest priority. In this way, accessibility to interrupt service tends to be statistically leveled for each of the competing devices.
The specific rotation method gives the user versatility by allowing the user to select which IRQ line is to receive the lowest priority, all other IRQ lines are then assigned sequentially (circularly) higher priorities.
From the foregoing description, it may be seen that PIC structures of the type described accommodate uniprocessor systems with multiple peripheral devices but do not accommodate multiprocessor systems with multiple shared peripheral devices to which the present invention is addressed.